Space Data Centers Database
Search and compare space data center projects and related orbital computing demonstrations, including developers, technical specifications, suppliers, agreements and milestones. Follow each commitment to its original announcement.
Catalog: 99 projects. 13 proposal / study · 35 development · 14 launched · 20 demonstrated · 4 operating · 10 historical · 3 uncertain. These are project classifications, not spacecraft counts or verified commercial capacity.
38 projects classified as launched, demonstrated or operating: 30 reviewed, 8 with review limits or awaiting review. Each project appears in one classification.
Linked view: QI2S onboard hyperspectral-processing research.
Columns & coverage
1 of 1 projects have values for the selected fields. 1–1 of 1 configuration rows shown. Projects without values are hidden.
— No verified value recorded · N/A Not applicable · TBD Not yet defined · Conflict Unresolved. Configurations remain separate. Hardware ratings and plans do not establish measured performance. Open Details & sources for evidence and coverage notes.
| Project / configuration | Compute hardware | Compute throughput | Memory / storage |
|---|---|---|---|
| QI2S onboard hyperspectral-processing researchQI2S FPGA laboratory prototypeElbit Systems Electro-Optics Elop-led FP7 consortiumProject status: Completed laboratory research | DiniGroup DNV7F1A board with Xilinx Virtex7 7VX690T-1 FPGAQI2S FPGA laboratory prototypeReported specificationreported laboratory configuration 16 emulated Tensilica RISC cores at 35 MHzQI2S FPGA laboratory prototypeReported specificationreported laboratory configuration | 560 MFLOPSQI2S FPGA laboratory prototypeReported specificationreported laboratory configuration | 8 GB DDR3 RAMQI2S FPGA laboratory prototypeReported specificationreported laboratory configuration |
Compute hardware: DiniGroup DNV7F1A board with Xilinx Virtex7 7VX690T-1 FPGA QI2S FPGA laboratory prototype. Final IPS board configuration and chassis/power supply. Full RC64 silicon was not installed. No generic FPGA power or product memory maximum is adopted. reported laboratory configuration. Included with these qualifications. Source observation: 2026-10-31. Supporting source ↗Compute hardware: 16 emulated Tensilica RISC cores at 35 MHz QI2S FPGA laboratory prototype. Report describes a partial emulation of RC64 architecture and I/O, not64 physical CEVA RC64 cores. reported laboratory configuration. Included with these qualifications. Source observation: 2026-10-31. Supporting source ↗Compute throughput: 560 MFLOPS QI2S FPGA laboratory prototype. MFLOPS reported for the 35 MHz downscaled FPGA platform. Precision and detailed operating/measurement basis are not supplied. This is not orbital performance. reported laboratory configuration. Included with these qualifications. Source observation: 2026-10-31. Supporting source ↗Memory / storage: 8 GB DDR3 RAM QI2S FPGA laboratory prototype. Final project board contains 8 GB DDR3. The socket's generic16 GB capacity is not installed memory, and this is not storage. reported laboratory configuration. Included with these qualifications. Source observation: 2026-10-31. Supporting source ↗ | |||
Technical specifications retain the source’s original units and evidence status. Hardware counts, compute rates and power are not equivalent; launched hardware does not establish demonstrated performance. Supplier counts include suppliers and hosts only, reflect current filters and cover this directory, not the entire market. “No record” means no disclosure captured; it does not mean the work is unawarded. Latest developments use source dates, not routine review or collection dates.