Space Data Centers Database
Search and compare space data center projects and related orbital computing demonstrations, including developers, technical specifications, suppliers, agreements and milestones. Follow each commitment to its original announcement.
Catalog: 125 projects. 13 proposal / study · 52 development · 15 launched · 22 demonstrated · 6 operating · 14 historical · 3 uncertain. These are project classifications, not spacecraft counts or verified commercial capacity.
43 projects classified as launched, demonstrated or operating: 33 reviewed, 10 with review limits or awaiting review. Each project appears in one classification.
Linked view: Microchip PIC64-HPSC spaceflight processor.
Columns & coverage
1 of 1 projects have values for the selected fields. 1–1 of 1 configuration rows shown. Projects without values are hidden.
— No verified value recorded · N/A Not applicable · TBD Not yet defined · Conflict Unresolved. Configurations remain separate. Hardware ratings and plans do not establish measured performance. Open Details & sources for evidence and coverage notes.
| Project / configuration | Compute hardware | Compute throughput | Memory / storage |
|---|---|---|---|
| Microchip PIC64-HPSC spaceflight processorPIC64-HPSC product-design ratingMicrochip Technology / NASA JPLProject status: Operational silicon and early radiation characterization | Ten 64-bit SiFive RISC-V cores, SMP/AMP, vector and AI/ML processingpic64-hpsc-familyReported specificationofficial development or product account Secure boot, cryptographic acceleration, post-quantum cryptography and anti-tamper featurespic64-hpsc-familyReported specificationofficial development or product account | Up to 1 TFLOP/s (bfloat16)PIC64-HPSC all-eight-application-core vector matrix-multiply product ratingReported specificationPlanned specification Up to 2 TOPS INT8 · INT8 statedPIC64-HPSC all-eight-application-core vector matrix-multiply product ratingReported specificationPlanned specification | Two DDR3-2133/DDR4-3200 interfaces, up to32GB per interface,72-bit ECC or optional80-bit multibit protectionPIC64-HPSC brochure product designReported specificationofficial product specification NAND/NOR flash, SRAM and MRAM interface supportPIC64-HPSC brochure product designReported specificationofficial product specification |
Compute throughput: Up to 1 TFLOP/s (bfloat16) PIC64-HPSC all-eight-application-core vector matrix-multiply product rating. Published product-design rating, not achieved orbital throughput. As-of is this review date. PDF prints revision10/24, DS00005391D. Arithmetic format and eight-core workload boundary retained. bfloat16 arithmetic, distinct from IEEE half precision. Planned specification. Included with these qualifications. Source observation: 2026-11-04. Supporting source ↗Compute throughput: Up to 2 TOPS INT8 · INT8 stated PIC64-HPSC all-eight-application-core vector matrix-multiply product rating. Published product-design rating, not achieved orbital throughput. As-of is this review date. PDF prints revision10/24, DS00005391D. Arithmetic format and eight-core workload boundary retained. INT8 arithmetic. Planned specification. Included with these qualifications. Source observation: 2026-11-04. Supporting source ↗Compute hardware: Ten 64-bit SiFive RISC-V cores, SMP/AMP, vector and AI/ML processing pic64-hpsc-family. Family page reports ten cores. Brochure specifies eight X280 application cores up to 1GHz with 512-bit vectors, plus an S7 system controller at 500MHz and a separate secure controller. Optional application-core lockstep, Unified/Split/Cache-Isolated modes. Product architecture, not a selected EarthTraq payload. official development or product account. Included with these qualifications. Source observation: 2026-11-04. Supporting source ↗Compute hardware: Secure boot, cryptographic acceleration, post-quantum cryptography and anti-tamper features pic64-hpsc-family. Product architecture, not an achieved mission-security certification. Brochure adds WorldGuard partitioning up to32 domains and a dedicated secure enclave. Source: https://ww1.microchip.com/downloads/aemDocuments/documents/MPU64/ProductDocuments/Brochures/PIC64-HPSC-Series-00005391.pdf official development or product account. Included with these qualifications. Source observation: 2026-11-04. Supporting source ↗Memory / storage: Two DDR3-2133/DDR4-3200 interfaces, up to32GB per interface,72-bit ECC or optional80-bit multibit protection PIC64-HPSC brochure product design. Interface support, not populated RAM or installed capacity. No aggregate mission RAM inferred. official product specification. Included with these qualifications. Source observation: 2026-11-04. Supporting source ↗Memory / storage: NAND/NOR flash, SRAM and MRAM interface support PIC64-HPSC brochure product design. Media interfaces only, not installed storage media or capacities. official product specification. Included with these qualifications. Source observation: 2026-11-04. Supporting source ↗ | |||
Technical specifications retain the source’s original units and evidence status. Hardware counts, compute rates and power are not equivalent; launched hardware does not establish demonstrated performance. Supplier counts include suppliers and hosts only, reflect current filters and cover this directory, not the entire market. “No record” means no disclosure captured; it does not mean the work is unawarded. Latest developments use source dates, not routine review or collection dates.