Europe / Israel · Named enabling processor research
MACSPACE manycore rad-hard DSP research
This project focuses on named enabling processor research.
MACSPACE was a 2013–2016 FP7 program to develop a non-dependent radiation-hard manycore DSP processor, software tools, FPGA prototype and prototype chip for space applications. CORDIS records a EUR2,495,048 EU contribution. Its proposal targets are not verified final performance or operating orbital capacity. MACSPACE is a distinct grant from QI2S, whose laboratory prototype drew on related RC64 component development.
Ramon.Space-led FP7 consortium · Closed historical research, final performance unverified
Scope: Enabling research · Named enabling processor/software and prototype research, without a defined shared service platform or operating mission.
Figures retain their disclosed units and scope. Launched hardware does not establish demonstrated performance; targets may change. Not disclosed means no figure in the reviewed sources.
PROJECT RELATIONSHIPS
Suppliers & project partners
CEVA Limited
Consortium participant
Program organization: European Commission
Partnership
Named MACSPACE consortium participant. The fact sheet does not establish a separate procurement order or individual hardware work package.
Historical FP7 research role. Canonical organization identity reused, including Thales Alenia Space for its named Italian entity. Consortium EU contribution counted once, not again through participant shares.
Announced Publication date not supplied · Evidence checked 31 Oct 2026
Named MACSPACE consortium participant. The fact sheet does not establish a separate procurement order or individual hardware work package.
Historical FP7 research role. Canonical organization identity reused, including Thales Alenia Space for its named Italian entity. Consortium EU contribution counted once, not again through participant shares.
Announced Publication date not supplied · Evidence checked 31 Oct 2026
Named MACSPACE consortium participant. The fact sheet does not establish a separate procurement order or individual hardware work package.
Historical FP7 research role. Canonical organization identity reused, including Thales Alenia Space for its named Italian entity. Consortium EU contribution counted once, not again through participant shares.
Announced Publication date not supplied · Evidence checked 31 Oct 2026
Named MACSPACE consortium participant. The fact sheet does not establish a separate procurement order or individual hardware work package.
Historical FP7 research role. Canonical organization identity reused, including Thales Alenia Space for its named Italian entity. Consortium EU contribution counted once, not again through participant shares.
Announced Publication date not supplied · Evidence checked 31 Oct 2026
MACSPACE coordinator, listed under historical name Ramon Chips Ltd.
Historical FP7 research role. Canonical organization identity reused, including Thales Alenia Space for its named Italian entity. Consortium EU contribution counted once, not again through participant shares.
Announced Publication date not supplied · Evidence checked 31 Oct 2026
Named MACSPACE consortium participant. The fact sheet does not establish a separate procurement order or individual hardware work package.
Historical FP7 research role. Canonical organization identity reused, including Thales Alenia Space for its named Italian entity. Consortium EU contribution counted once, not again through participant shares.
Announced Publication date not supplied · Evidence checked 31 Oct 2026
Named MACSPACE consortium participant. The fact sheet does not establish a separate procurement order or individual hardware work package.
Historical FP7 research role. Canonical organization identity reused, including Thales Alenia Space for its named Italian entity. Consortium EU contribution counted once, not again through participant shares.
Announced Publication date not supplied · Evidence checked 31 Oct 2026
Locate final technical deliverables or an official component-history account to reconcile achieved configuration with proposal objectives. No flight milestone is established.
Manual review with evidence gaps 31 Oct 2026. Compared the CORDIS grant, dates, seven organizations and objectives with QI2S's accepted downscaled prototype record. Published the distinct historical research program and grant. Reporting route supplied no final results. Proposed compute ratings remain held, with no flight assets or achieved performance inferred. Primary body last observed not available. Source monitoring: partial. Source collection and substantive profile review are separate checks. Plans and dates may change.
Final achieved processor configuration, qualification and benchmark results are not established by the inspected fact sheet. The reporting route returned the same fact sheet.
Proposal targets of 51.2 GOPS and 12.8 GFLOPS lack arithmetic precision and test conditions. They are not substituted for the differing RC64 targets retained with QI2S.
No launched MACSPACE mission, flight host, orbit or operating service is established. Research dates are not mission life.
Grant signature date is not supplied. Total cost EUR3,310,928.20 is distinct from the EU contribution and is not another financing event.
Project updates
Verified announcements and milestones linked to this project, newest first.
CORDIS records MACSPACE grant607212, a December2013–December2016 program led by Ramon Chips, with USD 2,787,468 (EUR2,495,048) EU support. Objectives included manycore DSP hardware, software, FPGA and radiation-hard chip prototypes. This historical entry uses the fact sheet last-update date of September1,2025.
